7.1.8
Master Latency Timer Register
Offset
x‘00D’
The Master Latency Timer register is implemented for legacy compatibility purposes but has
no impact on the 820x's functionality. This register is hard-wired to 0x00.
7.1.9
Header Type Register
Offset
x‘00E’
The Header Type register is a read-only optional register whose value is hard-wired to
0x00.
7.1.10
BIST Register
Offset
x‘00F’
The BIST register is used for control and status of the BIST function. This register is hard-
wired to 0x00.
820x – Data Sheet, DS-0157-D
Page210
Hifn Confidential