6.6.5
GPIO Interrupt Mask Register
The GPIO Interrupt Mask register is used to mask the GPIO interrupts. By default, all
interrupts bits are unmasked.
If a one is written to a bit in this register, that bit will be masked from generating an
interrupt. The host may be read this register to determine the masked/unmasked status of
each bit.
Type:
Offset
Read/Write
x‘0864’
Reserved
GPIO_INT_MASK[15:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Reset
Reserved
31:16
0
Reserved.
GPIO_INT_MASK
[15:0]
GPIO Interrupt Mask.
Each GPIO bit can be masked as:
15:0
0
0
1
Unmasked (default)
Masked
6.6.6
GPIO Interrupt Type Register
The GPIO Interrupt Type register controls whether the interrupt is level-sensitive or
otherwise edge-sensitive. Each bit may be independently set.
Type:
Offset
Read/Write
x‘0868’
Reserved
GPIO_INT_TYPE[15:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Reset
Reserved
31:16
0
Reserved.
GPIO_INT_TYPE
[15:0]
GPIO Interrupt Type.
Each GPIO bit can be set as:
15:0
0
0
1
Level-sensitive (default)
Edge-sensitive
820x – Data Sheet, DS-0157-D
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