Table 8-11. SDRAM Interface Timing
Tac
DQ access time from CK
DQS access time from CK
-700
-600
700
600
ps
ps
Tdqsck
Note
WL is the write latency of the DDR2 DRAM (in clock cycles). The Tdqss parameter indicates that the
edge of the DQS signal must be no more than +/- 0.25 of a clock period away from the appropriate
clock edge.
8.11 Flash Device Timing
The 4450 supports both reading and writing of SPI type Flash devices, up to a tbd MHz
clock rate. The Flash device interface signal timing is derived from an internal CPU toggling
GPIO pins. Additional details regarding the SPI interface via the esc_gpio[4:0] pins is
described in Section 6.7.
Table 8-12 and Figure 8-10 describe the read and write timing.
Table 8-12. Flash Device read and write Timing
Symbol
Twh
Twl
Parameter
Min
22
Max
Units
ns
Clock high period
Clock low period
CS high period
CS (setup) to Clock
Clock to CS (hold)
Read data valid
Read data hold
Read data hi-Z
Write data set up
Write data hold
22
ns
Tcs
250
250
250
ns
Tcss
Tcsh
Tv
ns
ns
20
20
ns
Tho
Tdis
Tsu
0
ns
ns
5
ns
Th
10
ns
Figure 8-10. Flash device read and write timing (SPI mode 0)
4450 – Data Sheet, DS-0131-06
Page78
Hifn Confidential
EXAR [ EXAR CORPORATION ]
