RXC
Rx_Ctl
Thld
Tdelay
DATA1
DATA2
DATAN
RXD[3:0]
Figure 8-7. RTBI Receive Signal Timing
8.7 RGMII Timing
Note that not all PHYs meet these RGMII timing requirements. Careful attention should be
given to the specific PHY specification and its possible board routing implications.
Table 8-8. RGMII Timing
Mode
Rise Time
(max)
Fall Time
(max)
Input Signals
Output Signals
Setup
Hold
1.00 ns
Setup
Hold
1.20 ns
RGMII
0.75 ns
0.75 ns
1.00 ns
1.20 ns
TXC
Tsu
Thld
DATA1
DATA2
DATAN
TXD[3:0]
Figure 8-8. RGMII Transmit Signal Timing
RXC
Rx_Ctl
Thld
Tdelay
DATA1
DATA2
DATAN
RXD[3:0]
Figure 8-9. RGMII Receive Signal Timing
4450 – Data Sheet, DS-0131-06
Page76
Hifn Confidential
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