EMD3D256M08BS1
EMD3D256M16BS1
FUNCTIONAL DESCRIPTION
Basic Functionality
The DDR3 STT-MRAM is a high-speed Spin-Torque Magnetoresistive Random Access Memory inter-
nally configured as an eight-bank RAM. It uses an 8n prefetch architecture to achieve high-speed
operation. The 8n prefetch architecture is combined with an interface designed to transfer two
data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 MRAM
consists of a single 8n-bit wide, four clock data transfer at the internal STT-MRAM core and two cor-
responding n-bit wide, one-half clock cycle data transfers at the I/O pins.
READ and write operations to the DDR3 STT-MRAM are burst oriented, start at a selected location,
and continue for a burst length of eight or a “chopped”burst of four in a programmed sequence.
Operation begins with the registration of an Active command, which is then followed by a READ
or WRITE command. The address bits registered coincident with the Active command are used to
select the bank and row to be activated ([BA0:BA2] select the bank; A0-A13 select the row); refer to
“Table 1 – Addressing Scheme by I/O Width”on page 9”for specific requirements. The address
bits registered coincident with the READ or WRITE command are used to select the starting column
location for the burst operation, determine if the auto precharge command is to be issued (via A10),
and select BC4 or BL8 mode ‘on the fly’(via A12) if enabled in the mode register.
Prior to normal operation, the DDR3 STT-MRAM must be powered up and initialized in a predefined
manner.
EMD3D256M08BS1/16BS1 Revision 1.3 10/2018
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