EtronTech
EM6GC16EWKE
Mode Register MR0
The mode-register MR0 stores data for controlling various operating modes of DDR3 SDRAM. It controls burst
length, read burst type, CAS latency, test mode, DLL reset, WR, and DLL control for precharge Power-Down, which
include various vendor specific options to make DDR3 DRAM useful for various applications. The mode register is
written by asserting low on CS#, RAS#, CAS#, WE#, BA0, BA1, and BA2, while controlling the states of address
pins according to the following figure.
Table 5. Mode Register Bitmap
BA2
BA1
BA0 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0 Address Field
BL Mode Register (0)
0*1
0
0
PPD WR
DLL TM
CAS Latency
RBT CL
BA1 BA0 MRS mode
A7 Mode
0 Normal
A3 Read Burst Type
0 Nibble Sequential
A1 A0
BL
8 (Fixed)
0
0
1
1
0
1
0
1
MR0
MR1
MR2
MR3
0
0
1
1
0
1
0
1
BC4 or 8 (on the fly)
BC4 (Fixed)
Reserved
1
Test
1
Interleave
A11 A10 A9
WR (cycles)
16*2
A6 A5 A4 A2
CAS Latency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
5*2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Reserved
6*2
7*2
8*2
10*2
12*2
14*2
5
6
7
8
9
10
11
12
13
A12 DLL Control for Precharge PD
0
1
Slow exit (DLL off)
Fast exit (DLL on)
DLL Reset
No
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
A8
0
1
Yes
Note 1: BA2 and A2 are reserved for future use and must be set to 0 when programming the MR.
Note 2: WR (write recovery for autoprecharge) min in clock cycles is calculated by dividing tWR (ns) by tCK (ns) and rounding
up to the next integer WRmin [cycles] =Roundup (tWR / tCK). The value in the mode register must be programmed to
be equal or larger than WRmin. The programmed WR value is used with tRP to determine tDAL.
Rev. 1.0
13
Jul. /2015
ETRON [ ETRON TECHNOLOGY, INC. ]
