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EM6AB080TSB-5G 参数 Datasheet PDF下载

EM6AB080TSB-5G图片预览
型号: EM6AB080TSB-5G
PDF下载: 下载PDF文件 查看货源
内容描述: [64M x 8 bit DDR Synchronous DRAM (SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 62 页 / 563 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
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EM6AB080  
EtronTech  
Table 16. Electrical Characteristics and Recommended A.C.Operating Condition  
(VDD = 2.5V ± 0.2V, TA = 0~70 °C)  
-4  
-5  
Symbol  
Parameter  
Unit Note  
Min.  
Max.  
-
Min.  
7.5  
6
Max.  
12  
CL = 2  
CL = 2.5  
CL = 3  
-
-
ns  
ns  
ns  
tCK  
tCK  
tCK  
Clock cycle time  
-
12  
4
12  
5
12  
tCH  
tCL  
Clock high level width  
Clock low level width  
0.45  
0.45  
0.55  
0.55  
0.45  
0.45  
0.55  
0.55  
t
CLMIN or  
tCHMIN  
t
CLMIN or  
tCHMIN  
tHP  
Clock half period  
-
-
ns  
2
tHZ  
tLZ  
Data-out-high impedance time from CK,  
Data-out-low impedance time from CK,  
-
0.7  
0.7  
0.6  
0.7  
-
0.7  
0.7  
0.6  
0.7  
ns  
ns  
ns  
ns  
3
3
CK  
CK  
-0.7  
-0.6  
-0.7  
-0.7  
-0.6  
-0.7  
tDQSCK DQS-out access time from CK,  
CK  
tAC  
Output access time from CK,  
CK  
tDQSQ  
tRPRE  
tRPST  
tDQSS  
DQS-DQ Skew  
Read preamble  
Read postamble  
CK to valid DQS-in  
-
0.4  
-
0.4  
ns  
tCK  
tCK  
tCK  
ns  
tCK  
tCK  
tCK  
tCK  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCK  
ns  
µs  
tCK  
ns  
ns  
ns  
ns  
ns  
tCK  
tCK  
0.9  
0.4  
0.8  
0
1.1  
0.9  
0.4  
0.72  
0
1.1  
0.6  
0.6  
1.2  
1.25  
tWPRES DQS-in setup time  
-
-
4
5
tWPRE  
tWPST  
tDQSH  
tDQSL  
tIS  
DQS Write preamble  
DQS write postamble  
0.25  
0.4  
0.35  
0.35  
0.7  
0.7  
0.4  
0.4  
-
0.25  
0.4  
0.35  
0.35  
0.7  
0.7  
0.4  
0.4  
-
0.6  
0.6  
DQS in high level pulse width  
DQS in low level pulse width  
-
-
-
-
Address and Control input setup time  
Address and Control input hold time  
DQ & DM setup time to DQS  
DQ & DM hold time to DQS  
DQ/DQS output hold time from DQS  
Row cycle time  
-
-
6
6
tIH  
-
-
tDS  
-
-
tDH  
-
-
tQH  
tHP - tQHS  
-
tHP - tQHS  
55  
-
tRC  
55  
70  
40  
15  
15  
8
-
-
tRFC  
tRAS  
tRCD  
tRP  
Refresh row cycle time  
-
70  
-
Row active time  
70K  
40  
70K  
Active to Read or Write delay  
Row precharge time  
-
15  
-
-
15  
-
tRRD  
tWR  
Row active to Row active delay  
Write recovery time  
-
10  
-
12  
2
-
15  
-
tWTR  
tMRD  
tREFI  
tXSRD  
tXSNR  
tDAL  
tDIPW  
tIPW  
tQHS  
tDSS  
tDSH  
Internal Write to Read Command Delay  
Mode register set cycle time  
Average Periodic Refresh interval  
Self refresh exit to read command delay  
-
2
-
8
-
10  
-
-
7.8  
-
7.8  
7
200  
75  
-
200  
75  
-
Self refresh exit to non-read command delay  
-
-
Auto Precharge write recovery + precharge time tWR+tRP  
-
tWR+tRP  
1.75  
2.2  
-
-
DQ and DM input pulse width  
Control and Address input pulse width  
Data Hold Skew Factor  
1.75  
2.2  
-
-
-
-
-
0.5  
-
0.5  
-
DQS falling edge to CK setup time  
DQS falling edge hold time from CK  
0.2  
0.2  
0.2  
0.2  
-
-
Etron Confidential  
12  
Rev.1.1  
Dec. /2013  
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