EtronTech
EM6AA160TSA
Table 18. SSTL _2 Interface
Reference Level of Output Signals (VREF
)
0.5 * VDDQ
Output Load
Reference to the Test Load
VREF+0.35 V / VREF-0.35 V
1 V/ns
Input Signal Levels
Input Signals Slew Rate
Reference Level of Input Signals
0.5 * VDDQ
Figure 3. SSTL_2 A.C. Test Load
0.5 x VDDQ
50Ω
DQ, DQS
Z0=50Ω
30pF
10) Power up Sequence
Power up must be performed in the following sequence.
1) Apply power to VDD before or at the same time as VDDQ, VTT and VREF when all input signals are held
"NOP" state and maintain CKE “LOW”.
2) Start clock and maintain stable condition for minimum 200µs.
3) Issue a “NOP” command and keep CKE “HIGH”
4) Issue a “Precharge All” command.
5) Issue EMRS – enable DLL.
6) Issue MRS – reset DLL. (An additional 200 clock cycles are required to lock the DLL).
7) Precharge all banks of the device.
8) Issue two or more Auto Refresh commands.
9) Issue MRS – with A8 to low to initialize the mode register.
Etron Confidential
14
Rev. 1.2
May 2009
ETRON [ ETRON TECHNOLOGY, INC. ]
