EtronTech
EM6AA160TSA
Table 17. Recommended A.C. Operating Conditions
(VDD = 2.5V ± 5%, TA = 0~70 °C)
Parameter
Input High Voltage (AC)
Symbol
VIH (AC)
VIL (AC)
VID (AC)
Min.
Max.
-
Unit
V
VREF + 0.35
Input Low Voltage (AC)
-
VREF – 0.35
VDDQ + 0.6
V
0.7
V
Input Different Voltage, CK and
inputs
CK
VIX (AC)
inputs
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
Input Crossing Point Voltage, CK and
CK
Note:
1) Enables on-chip refresh and address counters.
2) Min(tCL, tCH) refers to ther smaller of the actual clock low time and actual clock high time as provided to the
device.
3) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters
are not referenced to a specific voltage level, but specify when the device output is no longer driving(HZ), or
begins driving(LZ).
4) The specific requirement is that DQS be valid (High, Low, or at some point on a valid transition) on or
before this CK edge. A valid transition is defined as monotonic, and meeting the input slew rate
specifications of the device. When no writes were previously in progress on the bus, DQS will be
transitioning from High-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or
transitioning from HIGH to LOW at this time, depending on tDQSS.
5) The maximum limit for this parameter is not a device limit. The device will operate with a greater value for
this parameter, but system performance (bus turnaround) will degrade accordingly.
≧
1.0V/ns.
6) For command/address and CK &
slew rate
CK
7) A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
8) Power-up sequence is described in Note 10
9) A.C. Test Conditions
Etron Confidential
13
Rev. 1.2
May 2009
ETRON [ ETRON TECHNOLOGY, INC. ]
