EtronTech
EM6AA320
8Mx32 DDR SDRAM
Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 2.8V 5%, T = 0~70 C)
±
°
A
3.3
3.6
4.0
5.0
Symbol
Parameter
Unit
Min
-
Max
-
Min
-
Max
-
Min
4
Max
10
Min
5
Max
10
CL = 3
CL = 4
Clock cycle time
tCK
ns
3.3
10
3.6
10
4
10
5
10
Clock high level width
Clock low level width
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55
tCH
tCL
tDQSCK
tAC
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ns
ns
tCK
tCK
tCK
ns
ns
ns
ns
DQS-out access time from CK,CK#
Output access time from CK,CK#
DQS-DQ Skew
-0.6
-0.6
-
0.6
0.6
-0.6
-0.6
-
0.6
0.6
0.4
1.1
0.6
-0.7
-0.7
-
0.7
0.7
0.4
1.1
0.6
-0.7
-0.7
-
0.7
0.7
0.35
1.1
0.45
1.1
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPREH
tWPST
tDQSH
tDQSL
tIS
Read preamble
0.9
0.4
0.9
0.4
0.9
0.4
0.9
0.4
Read postamble
0.6
0.6
CK to valid DQS-in
0.85 1.15 0.85 1.15 0.85 1.15 0.85 1.15
DQS-in setup time
0
-
-
0
-
-
0
-
-
0
-
-
DQS-in hold time
0.35
0.4
0.35
0.4
0.4
0.4
0.9
0.9
0.4
0.4
0.35
0.4
0.35
0.4
0.4
0.4
1.0
1.0
0.5
0.5
DQS write postamble
0.6
0.6
0.6
-
0.6
0.6
0.6
-
0.6
0.6
0.6
-
0.6
0.6
0.6
-
DQS in high level pulse width
DQS in low level pulse width
Address and Control input setup time
Address and Control input hold time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
0.4
0.4
0.4
0.4
0.9
0.9
0.9
-
-
0.9
-
-
tIH
tDS
tDH
0.35
0.35
-
-
0.45
0.45
-
-
-
-
-
-
tCLMIN
or
tCHMIN
tCLMIN
or
tCHMIN
tCLMIN
or
tCHMIN
tCLMIN
or
tCHMIN
Clock half period
-
-
-
-
tHP
ns
tHP -
0.35
tHP -
0.4
tHP -
0.45
tHP -
0.5
Output DQS valid window
-
-
-
-
tQH
ns
Row cycle time
17
19
12
6
-
16
18
11
5
-
15
17
10
5
-
12
14
8
-
tRC
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
Refresh row cycle time
-
-
-
-
tRFC
tRAS
tRCDRD
tRCDWR
tRP
tRRD
twR
tCDLR
tCCD
tMRD
tDAL
Row active time
100K
100K
100K
100K
RAS# to CAS# Delay in Read
RAS# to CAS# Delay in Write
Row precharge time
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4
-
-
-
-
-
-
-
-
-
-
4
3
3
2
5
3
3
3
Row active to Row active delay
Write recovery time
3
3
3
2
3
3
3
2
Last data in to Read command
Col. Address to Col. Address delay
Mode register set cycle time
Auto precharge write recovery + Precharge
Self refresh exit to read command delay
2
2
2
2
1
1
1
1
1
1
2
2
9
9
8
7
200
200
200
200
tXSA
tIS +
2tCK
tIS +
2tCK
tIS +
2tCK
tIS +
2tCK
Power down exit time
Refresh interval time
-
-
-
-
tPDEX
tREF
ns
us
-
7.8
7.8
-
7.8
7.8
12
Rev 0.6
May 2006
ETRON [ ETRON TECHNOLOGY, INC. ]
