EtronTech
EM6AA320
8Mx32 DDR SDRAM
Decoupling Capacitance Guide Line
Symbol
Parameter
Value
0.1+0.01
0.1+0.01
Unit
uF
uF
CDC1 Decouping Capacitance between VDD and VSS
CDC2 Decouping Capacitance between VDDQ and VSSQ
AC Input Operating Conditions
(VDD = 2.8V ± 5%, TA = 0~70 °C)
Symbol
VIH
Parameter
Input High Voltage; DQ
Min
VREF+0.4
Max
-
Unit
V
Note
VIL
VID
VIX
Input Low Voltage; DQ
Clock Input Differential Voltage; Ck & CK#
Clock Input Crossing Point Voltage; Ck & CK#
-
VREF-0.4
VDDQ+0.6
V
V
V
0.8
0.5xVDDQ-0.2 0.5xVDDQ+0.2
AC Operating Test Conditions
(VDD = 2.8V ± 5%, TA = 0~70 °C)
Reference Level of Output Signals (VRFE
CK & CK# signal maximum peak swing
Output Load
Input Signal Levels
Input Signals Slew Rate
)
0.5 x VDDQ
1.5V
See Figure. A Test Load
VREF+0.4 V / VREF-0.4 V
1 V/ns
Input timing measurement reference level
Output timing measurement reference level
Reference Level of Input Signals
VREF
VTT
0.5 x VDDQ
Figure A. Test Load
VTT=0.5 x VDDQ
50Ω
DQ,DQS
Z0=50 W
30pF
VREF=0.5 x VDDQ
11
Rev 0.6
May 2006
ETRON [ ETRON TECHNOLOGY, INC. ]
