EtronTech
Extended Mode Register Set (EMRS)
EM6A9160TSA
The Extended Mode Register Set stores the data for enabling or disabling DLL and selecting output driver strength.
The default value of the extended mode register is not defined, therefore must be written after power up for proper
operation. The extended mode register is written by asserting low on
CS
,
RAS
,
CAS
, and
WE
. The state of A0,
A2 ~ A5, A7 ~ A11and BA1 is written in the mode register in the same cycle as
CS
,
RAS
,
CAS
, and
WE
going low.
The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode
register. A1 and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles
are required to complete the write operation in the extended mode register. The mode register contents can be
changed using the same command and clock cycle requirements during operation as long as all banks are in the
idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. Refer to the table for specific
codes.
Table 11. Extended Mode Register Bitmap
BA1 BA0 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Field
0
1
RFU must be set to “0”
DS1 RFU must be set to “0” DS0 DLL Extended Mode Register
BA0 Mode
0
MRS
1
EMRS
A6 A1
Drive Strength
Comment
0
0
Full
0
1
Weak
1
0
RFU
Reserved For Future
1
1 Matched impedance Output driver matches impedance
A0
0
1
DLL
Enable
Disable
Etron Confidential
9
Rev. 1.1
Aug. 2009
ETRON [ ETRON TECHNOLOGY, INC. ]
