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EM6A9160TSA-4G 参数 Datasheet PDF下载

EM6A9160TSA-4G图片预览
型号: EM6A9160TSA-4G
PDF下载: 下载PDF文件 查看货源
内容描述: 8M ×16的DDR同步DRAM (SDRAM)的 [8M x 16 DDR Synchronous DRAM (SDRAM)]
分类和应用: 内存集成电路光电二极管动态存储器双倍数据速率
文件页数/大小: 51 页 / 438 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
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EM6A9160TSA  
EtronTech  
Table 16. Electrical AC Characteristics  
(VDD = 2.5V ± 5%, TA = 0~70 °C)  
-4  
Symbol  
Parameter  
Unit  
Max.  
Min.  
tCK  
tCH  
tCL  
Clock cycle time  
CL = 3  
4
10  
ns  
tCK  
tCK  
Clock high level width  
Clock low level width  
0.45  
0.45  
0.55  
0.55  
tDQSCK DQS-out access time from CK,  
-0.6  
-0.6  
0.6  
0.6  
ns  
ns  
CK  
tAC  
Output access time from CK,  
CK  
tDQSQ  
tRPRE  
tRPST  
tDQSS  
DQS-DQ Skew  
Read preamble  
Read postamble  
CK to valid DQS-in  
-
0.4  
ns  
tCK  
tCK  
tCK  
ns  
0.9  
1.1  
0.4  
0.6  
0.85  
1.15  
tWPRES DQS-in setup time  
0
-
tWPRE  
tWPST  
tDQSH  
tDQSL  
DQS write preamble  
0.35  
-
tCK  
tCK  
tCK  
tCK  
DQS write postamble  
0.4  
0.6  
DQS in high level pulse width  
DQS in low level pulse width  
0.4  
0.6  
0.4  
0.6  
Fast slew rate  
Slow slew rate  
Fast slew rate  
Slow slew rate  
0.6  
-
tIS  
tIH  
Address and Control input setup time  
Address and Control input hold time  
0.7  
-
ns  
0.6  
-
0.7  
-
tDS  
DQ & DM setup time to DQS  
DQ & DM hold time to DQS  
Clock half period  
0.4  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tDH  
0.4  
-
tHP  
tCLMIN or tCHMIN  
-
tQH  
DQ/DQS output hold time from DQS  
Row cycle time  
tHP - tQHS  
-
tRC  
52  
70  
-
tRFC  
tRAS  
tRCD  
tRP  
Refresh row cycle time  
Row active time  
-
36  
70K  
Active to Read or Write Delay  
Row precharge time  
16  
-
-
-
-
-
16  
tRRD  
tWR  
Row active to Row active delay  
Write recovery time  
12  
12  
tMRD  
tCCD  
tDAL  
tXSRD  
tPDEX  
tREFI  
tIPW  
tDIPW  
Mode register set cycle time  
Col. Address to Col. Address delay  
2
tCK  
tCK  
tCK  
tCK  
ns  
µs  
ns  
ns  
1
Auto precharge write recovery + Precharge time  
Self refresh exit to read command delay  
Power down exit time  
7
-
200  
tCK + tIS  
-
-
-
15.6  
-
Refresh interval time  
Cntrol and Address input pulse width  
DQ & DM input pulse width (for each input)  
2.2  
1.75  
-
tHZ  
Data-out high-impedance window from CK,  
-
0.7  
ns  
CK  
tLZ  
Data-out low-impedance window from CK,  
Data Hold Skew Factor  
-0.7  
-
0.7  
ns  
ns  
CK  
tQHS  
tDSS  
tDSH  
tWTR  
tXSNR  
0.4  
DQS falling edge to CK rising – setup time  
DQS falling edge to CK rising – hold time  
Internal Write to Read command delay  
Exit Self-Refresh to non-Read command  
0.2  
0.2  
2
-
-
-
-
tCK  
tCK  
tCK  
ns  
75  
Etron Confidential  
12  
Rev. 1.1  
Aug. 2009