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EM6A9320BI-5M 参数 Datasheet PDF下载

EM6A9320BI-5M图片预览
型号: EM6A9320BI-5M
PDF下载: 下载PDF文件 查看货源
内容描述: 4M ×32 DDR SDRAM [4M x 32 DDR SDRAM]
分类和应用: 内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 17 页 / 354 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
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EtronTech  
EM6A9320BI  
Electrical Characteristics and Recommended A.C. Operating Conditions  
4Mx32 DDR SDRAM  
(VDD = 2.5V ± 5%, Ta = 0~70 °C)  
4
5
6
Symbol  
Parameter  
Unit  
Min  
Max  
-
Min  
75  
6
Max  
10  
Min  
75  
6
Max  
12  
CL = 2  
CL = 2.5  
CL = 3  
-
-
Clock cycle time  
-
10  
12  
tCK  
ns  
4
10  
0.55  
5
10  
6
12  
Clock high level width  
Clock low level width  
0.45  
0.45  
0.55  
0.45  
0.55  
tCH  
tCL  
tDQSCK  
tAC  
tCK  
tCK  
ns  
ns  
ns  
tCK  
tCK  
tCK  
ns  
tck  
tCK  
tCK  
tCK  
ns  
0.45  
-0.7  
-0.7  
-
0.55  
0.7  
0.7  
0.4  
1.1  
0.6  
1.15  
-
0.45  
-0.7  
-0.7  
-
0.55  
0.7  
0.7  
0.4  
1.1  
0.6  
1.2  
-
0.45  
-0.7  
-0.7  
-
0.55  
0.7  
0.7  
0.45  
1.1  
0.6  
1.25  
-
DQS-out access time from CK,CK#  
Output access time from CK,CK#  
DQS-DQ Skew  
tDQSQ  
tRPRE  
tRPST  
tDQSS  
tWPRES  
tWPREH  
tWPST  
tDQSH  
tDQSL  
tIS  
Read preamble  
0.9  
0.4  
0.85  
0
0.9  
0.4  
0.8  
0
0.9  
0.4  
0.75  
0
Read postamble  
CK to valid DQS-in  
DQS-in setup time  
DQS-in hold time  
0.35  
0.4  
0.4  
0.4  
0.9  
0.9  
0.45  
0.45  
-
0.25  
0.4  
0.4  
0.4  
1.0  
1.0  
0.5  
0.5  
-
0.25  
0.4  
0.4  
0.4  
1.0  
1.0  
0.5  
0.5  
-
DQS write postamble  
0.6  
0.6  
0.6  
-
0.6  
0.6  
0.6  
-
0.6  
0.6  
0.6  
-
DQS in high level pulse width  
DQS in low level pulse width  
Address and Control input setup time  
Address and Control input hold time  
DQ & DM setup time to DQS  
DQ & DM hold time to DQS  
-
-
-
tIH  
tDS  
tDH  
ns  
ns  
ns  
-
-
-
-
-
-
tCLMIN or  
tCHMIN  
tCLMIN or  
tCHMIN  
tCLMIN or  
tCHMIN  
Clock half period  
-
-
-
tHP  
ns  
Data hold skew factor  
-
0.45  
-
0.5  
0.55  
tQHS  
tQH  
tRC  
tRFC  
tRAS  
tRCDRD  
tRCDWR  
tRP  
ns  
ns  
Output DQS valid window  
Row cycle time  
-
-
-
tHP - tQHS  
tHP - tQHS  
tHP - tQHS  
15  
-
12  
-
10  
-
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
ns  
Refresh row cycle time  
Row active time  
17  
-
14  
-
12  
-
10  
100K  
8
100K  
7
100K  
RAS# to CAS# Delay in Read  
RAS# to CAS# Delay in Write  
Row precharge time  
5
-
4
-
3
-
3
-
2
-
2
-
4
-
4
-
3
-
Row active to Row active delay  
Write recovery time  
3
-
2
-
2
-
tRRD  
twR  
3
-
2
-
2
-
Last data in to Read command  
Col. Address to Col. Address delay  
Mode register set cycle time  
Auto precharge write recovery + Precharge  
Self refresh exit to read command delay  
Power down exit time  
2
-
2
-
2
-
tCDLR  
tCCD  
tMRD  
tDAL  
tXSA  
tPDEX  
tREF  
tJ  
1
-
1
-
1
-
2
-
-
2
-
-
2
-
-
7
6
6
200  
-
200  
-
200  
-
tIS + 2tCK  
-
tIS + 2tCK  
-
tIS + 2tCK  
-
Refresh interval time  
-
-
-
7.8  
100  
700  
-
-
-
7.8  
105  
700  
-
-
-
7.8  
105  
700  
us  
ps  
ps  
Short term jitter  
CLK Rise time, Fall time  
tR, tF  
12  
Rev 0.9C  
May 2006