EtronTech
EM68C08CWAG
Input clock frequency change during precharge power down
DDR2 SDRAM input clock frequency can be changed under following condition: DDR2 SDRAM is in precharged
power down mode. ODT must be turned off and CKE must be at logic LOW level. A minimum of 2 clocks must be
waited after CKE goes LOW before clock frequency may change. SDRAM input clock frequency is allowed to
change only within minimum and maximum operating frequency specified for the particular speed grade. During
input clock frequency change, ODT and CKE must be held at stable LOW levels. Once input clock frequency is
changed, stable new clocks must be provided to DRAM before precharge power down may be exited and DLL must
be RESET via EMRS after precharge power down exit. Depending on new clock frequency an additional MRS
command may need to be issued to appropriately set the WR, CL etc. During DLL re-lock period, ODT must remain
off. After the DLL lock time, the DRAM is ready to operate with new clock frequency.
No operation command
The No Operation Command should be used in cases when the DDR2 SDRAM is in an idle or a wait state. The
purpose of the No Operation Command (NOP) is to prevent the DDR2 SDRAM from registering any unwanted
commands between operations. A No Operation Command is registered when CS# is LOW with RAS#, CAS#, and
WE# held HIGH at the rising edge of the clock. A No Operation Command will not terminate a previous operation
that is still executing, such as a burst read or write cycle.
Deselect command
The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs
when CS# is brought HIGH at the rising edge of the clock, the RAS#, CAS#, and WE# signals become don’t cares.
Rev. 1.1
22
Apr. /2016
ETRON [ ETRON TECHNOLOGY, INC. ]
