EtronTech
EM68C08CWAG
Self refresh operation
The Self Refresh command can be used to retain data in the DDR2 SDRAM, even if the rest of the system is
powered down. When in the Self Refresh mode, the DDR2 SDRAM retains data without external clocking. The
DDR2 SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is
defined by having CS#, RAS#, CAS# and CKE# held LOW with WE# HIGH at the rising edge of the clock. ODT
must be turned off before issuing Self Refresh command, by either driving ODT pin LOW or using EMRS command.
Once the Command is registered, CKE must be held LOW to keep the device in Self Refresh mode. The DLL is
automatically disabled upon entering Self Refresh and is automatically enabled upon exiting Self Refresh. When the
DDR2 SDRAM has entered Self Refresh mode all of the external signals except CKE, are “don’t care”. For proper
Self Refresh operation all power supply pins (VDD, VDDQ, VDDL and VREF) must be at valid levels. The DRAM
initiates a minimum of one refresh command internally within tCKE period once it enters Self Refresh mode. The
clock is internally disabled during Self Refresh Operation to save power. The minimum time that the DDR2 SDRAM
must remain in Self Refresh mode is tCKE. The user may change the external clock frequency or halt the external
clock one clock after Self Refresh entry is registered, however, the clock must be restarted and stable before the
device can exit Self Refresh operation.
The procedure for exiting Self Refresh requires a sequence of commands. First, the clock must be stable prior to
CKE going back HIGH. Once Self Refresh Exit is registered, a delay of at least tXSNR must be satisfied before a
valid command can be issued to the device to allow for any internal refresh in progress. CKE must remain HIGH for
the entire Self Refresh exit period tXSRD for proper operation except for Self Refresh re-entry. Upon exit from Self
Refresh, the DDR2 SDRAM can be put back into Self Refresh mode after waiting at least tXSNR period and issuing
one refresh command(refresh period of tRFC). NOP or Deselect commands must be registered on each positive
clock edge during the Self Refresh exit interval tXSNR. ODT should be turned off during tXSRD. The use of Self
Refresh mode introduces the possibility that an internally timed refresh event can be missed when CKE is raised for
exit from Self Refresh mode. Upon exit from Self Refresh, the DDR2 SDRAM requires a minimum of one extra auto
refresh command before it is put back into Self Refresh mode.
Power-Down
Power-down is synchronously entered when CKE is registered LOW along with NOP or Deselect command. No read
or write operation may be in progress when CKE goes LOW. These operations are any of the following: read burst or
write burst and recovery. CKE is allowed to go LOW while any of other operations such as row activation, precharge
or autoprecharge, mode register or extended mode register command time, or autorefresh is in progress.
The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting
power-down mode for proper read operation.
If power-down occurs when all banks are precharged, this mode is referred to as Precharge Power-down; if power-
down occurs when there is a row active in any bank, this mode is referred to as Active Power-down. For Active
Power-down two different power saving modes can be selected within the MRS register, address bit A12. When A12
is set to “LOW” this mode is referred as “standard active power-down mode” and a fast power-down exit timing
defined by the tXARD timing parameter can be used. When A12 is set to “HIGH” this mode is referred as a power
saving “LOW power active power-down mode”. This mode takes longer to exit from the power-down mode and the
tXARDS timing parameter has to be satisfied. Entering power-down deactivates the input and output buffers,
excluding CK, CK#, ODT and CKE. Also the DLL is disabled upon entering precharge power-down or slow exit
active power-down, but the DLL is kept enabled during fast exit active power-down. In power-down mode, CKE LOW
and a stable clock signal must be maintained at the inputs of the DDR2 SDRAM, and all other input signals are
“Don’t Care”. Power-down duration is limited by 9 times tREFI of the device.
The power-down state is synchronously exited when CKE is registered HIGH (along with a NOP or Deselect
command). A valid, executable command can be applied with power-down exit latency, tXP, tXARD or tXARDS,
after CKE goes HIGH. Power-down exit latencies are defined in the AC spec table of this data sheet.
Asynchronous CKE LOW Event
DRAM requires CKE to be maintained “HIGH” for all valid operations as defined in this datasheet. If CKE
asynchronously drops “LOW” during any valid operation DRAM is not guaranteed to preserve the contents of array.
If this event occurs, memory controller must satisfy DRAM timing specification tDelay before turning off the clocks.
Stable clocks must exist at the input of DRAM before CKE is raised “HIGH” again. DRAM must be fully re-initialized.
DRAM is ready for normal operation after the initialization sequence.
Rev. 1.1
21
Apr. /2016
ETRON [ ETRON TECHNOLOGY, INC. ]
