EtronTech
EM68C08CWAE
Table 6-2. Extended Mode Register EMR (1) Bitmap
A11
A10
RDQS
/DM
RDQS#
DQS
DQS#
(RDQS Enable)
(DQS# Enable)
0(Disable)
0(Disable)
1(Enable)
1(Enable)
0(Enable)
1(Disable)
0(Enable)
1(Disable)
DM
DM
RDQS
RDQS
Hi-z
Hi-z
RDQS#
Hi-z
DQS
DQS
DQS
DQS
DQS#
Hi-z
DQS#
Hi-z
EMR(2)
The extended mode register (2) controls refresh related features. The default value of the extended mode register
(2) is not defined, therefore the extended mode register (2) must be written after power-up for proper operation. The
extended mode register(2) is written by asserting LOW on CS#, RAS#, CAS#, WE#, HIGH on BA1 and LOW on
BA0, while controlling the states of address pins A0 ~ A13. The DDR2 SDRAM should be in all bank precharge with
CKE already HIGH prior to writing into the extended mode register (2). The mode register set command cycle time
(tMRD) must be satisfied to complete the write operation to the extended mode register (2). Mode register contents
can be changed using the same command and clock cycle requirements during normal operation as long as all
banks are in the precharge state.
Table 7. Extended Mode Register EMR (2) Bitmap
BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field
0*1
1
0
0*1
0*1
PASR*3
SRF
DCC
Extended Mode Register(2)
A7
0
High Temperature Self-Refresh Rate Enable
Disable
Enable *2
1
BA1 BA0 MRS mode
A3
0
DCC Enable (Optional) *4
Disable
0
0
1
1
0
1
0
1
MR
EMR(1)
EMR(2)
EMR(3)
1
Enable
A2
0
A1
0
A0 Partial Array Self Refresh for 8 Banks (Optional)
0
1
0
1
0
1
0
1
Full array
0
0
Half Array (BA[2:0]=000,001,010&011)
Quarter Array (BA[2:0]= 000&001)
1/8 array (BA[2:0]=000)
0
1
0
1
1
0
3/4 array (BA[2:0]=010,011,100,101,110&111)
Half array (BA[2:0]= 100,101,110&111)
Quarter array (BA[2:0]= 110&111)
1/8 array (BA[2:0]=111)
1
0
1
1
1
1
NOTE 1: BA2 and A4-A6, A8-A13 is reserved for future use and must be set to 0 when programming the EMR(2).
NOTE 2: Due to the migration nature, user needs to ensure the DRAM part supports higher than 85 C Tcase temperature
°
self-refresh entry. If the high temperature self-refresh mode is supported then controller can set the EMRS2[A7] bit
to enable the self-refresh rate in case of higher than 85 C temperature self-refresh operation.
°
NOTE 3: If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will
be lost if self refresh is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh
command is issued.
NOTE 4: DCC (Duty Cycle Corrector) implemented, user may be given the controllability of DCC thru EMR (2) [A3] bit.
Rev. 1.3
11
Oct. /2015
ETRON [ ETRON TECHNOLOGY, INC. ]
