EM68B16DVAA
EtronTech
Figure 37. Power-Down Entry and Exit
CK
CK
tRP
tCKE
tXP
CKE
PRE
NOP
NOP
NOP
NOP
NOP
Valid
Valid
Valid
Command
Address
Pre All
A10 (AP)
DQ
High-Z
Power Down
Entry
Exit From
Power Down
Any
Command
Precharge Power-Down mode shown: all banks are idle and tRP is met
when Power-Down Entry command is issued
Don’t Care
Figure 38. Deep Power-Down Entry and Exit
T0
T1
Ta0
Ta1
Ta2
CK
CK
CKE
NOP
DPD
NOP
Valid
Valid
Command
Address
DQS
DQ
DM
T = 200µs
Exit DPD Mode
tRP
Enter DPD Mode
Don’t Care
(1) Clock must be stable before exiting Deep Power-Down mode. That is, the clock must be cycling
within specifications by Ta0
(2) Device must be in the all banks idle state prior to entering Deep Power-Down mode
(3) 200µs is required before any command can be applied upon exiting Deep Power-Down mode
(4) Upon exiting Deep Power-Down mode a PRECHARGE ALL command must be issued, followed
by two AUTO REFRESH commands and a load mode register sequence
Etron Confidential
39
Rev. 1.0
Mar. 2009
ETRON [ ETRON TECHNOLOGY, INC. ]
