EtronTech
Functional Description
EM68932DVKA
This 128Mb Mobile DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728
bits. It is internally configured as a quad-bank DRAM. Each of the 33,554,432-bit banks is organized as 4,096 rows by
256 columns by 32 bits. The 128Mb Mobile DDR SDRAM uses a double data rate architecture to achieve high speed
operation. EM68932D is applied to reduce leakage and refresh currents while achieving very high speed. The double
data rate architecture is essentially a 2n-prefetch architecture, with an interface designed to transfer two data words
per clock cycle at the I/O balls. Single read or write access for the 128Mb Mobile DDR SDRAM consists of a single 2n-
bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-
cycle data transfers at the I/O balls.
Read and write accesses to the Mobile DDR SDRAM are burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a programmed sequence. Accesses begin with an Active command,
which is then followed by a Read or Write command. The address bits registered coincident with the Active command
are used to select the bank and row to be accessed (BA0, BA1 select the bank, A0-A11 select the row). The address
bits (BA0, BA1 select the bank, A0-A7 select the column) registered coincident with the READ or WRITE command
are used to select the starting column location for the burst access.
Note that the DLL (Delay Lock Loop) circuitry used on standard DDR devices is not included in the Mobile DDR
SDRAM. It has been omitted to save power.
Prior to normal operation, the Mobile DDR SDRAM must be initialized.
Power-Up and Initialization
Mobile DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other
than those specified may result in undefined operation. To properly initialize the Mobile DDR SDRAM, this
sequence must be followed:
1. To prevent device latch-up, it is recommended that core power (V
DD
) and I/O power (V
DDQ
) be from the same
power source and be brought up simultaneously. If separate power sources are used, V
DD
must lead V
DDQ
.
2. Once power supply voltages are stable and CKE has been driven High, it is safe to apply the clock.
3. Once the clock is stable, a 200µs (minimum) delay is required by the Mobile DDR SDRAM prior to applying an
executable command. During this time, NOP or Deselect commands must be issued on the command bus.
4. Issue a Precharge All command.
5. Issue NOP or Deselect commands for at least t
RP
time.
6. Issue an Auto Refresh command followed by NOP or Deselect commands for at least t
RFC
time. Issue a second
Auto Refresh command followed by NOP or Deselect commands for at least t
RFC
time. As part of the
individualization sequence, two Auto Refresh commands must be issued. Typically, both of these commands
are issued at this stage as described above. Alternately, the second Auto Refresh command and NOP or
Deselect sequence can be issued between steps 10 and 11.
7. Using the Mode Register Set command, load the standard Mode Register as desired.
8. Issue NOP or Deselect commands for at least t
MRD
time.
9. Using the Mode Register Set command, load the Extended Mode Register to the desired operating modes. Note
that the sequence in which the standard and extended mode registers are programmed is not critical.
10. Issue NOP or Deselect commands for at least t
MRD
time.
11. The Mobile DDR SDRAM has been properly initialized and is ready to receive any valid command
.
Etron Confidential
6
Rev. 1.0
Mar. 2009
ETRON [ ETRON TECHNOLOGY, INC. ]
