EtronTech
EM68916CWQA
z Write data mask
One Write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDRAMs, Consistent
with the implementation on DDR SDRAMs. It has identical timings on Write operations as the data bits, and
though used in a uni-directional manner, is internally loaded identically to data bits to insure matched
system timing. DM is not used during read cycles.
z Precharge operation
The Precharge command is used to precharge or close a bank that has been activated. The Precharge
Command is triggered when CS#, RAS# and WE# are LOW and CAS# is HIGH at the rising edge of the
clock. The Precharge Command can be used to precharge each bank independently or all banks
simultaneously. Three address bits A10, BA1, and BA0 are used to define which bank to precharge when
the command is issued.
Table 13.Bank Selection for Precharge by address bits
A10
BA1
BA0
Precharged Bank(s)
LOW
LOW
LOW
LOW
HIGH
LOW
LOW
HIGH
LOW
HIGH
LOW
Bank 0 only
Bank 1 only
Bank 2 only
Bank 3 only
ALL Banks
HIGH
HIGH
DON’T CARE
DON’T CARE
z Burst read operation followed by precharge
Minimum Read to precharge command spacing to the same bank = AL + BL/2 + max (RTP, 2) - 2 clocks.
For the earliest possible precharge, the precharge command may be issued on the rising edge which
“Additive latency (AL) + BL/2 clocks” after a Read command. A new bank active (command) may be issued
to the same bank after the RAS# precharge time (tRP). A precharge command cannot be issued until tRAS is
satisfied.
The minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock
edge that initiates the last 4-bit prefetch of a Read to Precharge command. This time is called tRTP (Read to
Precharge). For BL = 4 this is the time from the actual read (AL after the Read command) to Precharge
command. For BL = 8 this is the time from AL + 2 clocks after the Read to the Precharge command.
z Burst Write operation followed by precharge
Minimum Write to Precharge command spacing to the same bank = WL + BL/2 + tWR. For write cycles, a
delay must be satisfied from the completion of the last burst write cycle until the Precharge command can
be issued. This delay is known as a write recovery time (tWR) referenced from the completion of the burst
write to the Precharge command. No Precharge command should be issued prior to the tWR delay, as
DDR2 SDRAM does not support any burst interrupt by a Precharge command. tWR is an analog timing
parameter and is not the programmed value for tWR in the MRS.
z Auto precharge operation
Before a new row in an active bank can be opened, the active bank must be precharged using either the
Precharge Command or the auto-precharge function. When a Read or a Write Command is given to the
DDR2 SDRAM, the CAS# timing accepts one extra address, column address A10, to allow the active bank to
automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is
LOW when the READ or WRITE Command is issued, then normal Read or Write burst operation is executed
and the bank remains active at the completion of the burst sequence. If A10 is HIGH when the Read or Write
Command is issued, then the auto-precharge function is engaged. During auto-precharge, a Read Command
will execute as normal with the exception that the active bank will begin to precharge on the rising edge which
is CAS# latency clock cycles before the end of the read burst. Auto-precharge also be implemented during
Write commands.The precharge operation engaged by the Auto precharge command will not begin until the
last data of the burst write sequence is properly stored in the memory array. This feature allows the
precharge operation to be partially or completely hidden during burst Read cycles (dependent upon CAS#
latency) thus improving system performance for random data access. The RAS# lockout circuit internally
delays the Precharge operation until the array restore operation has been completed (tRAS satisfied) so that
the auto precharge command may be issued with any Read or Write command.
Etron Confidential
18
Rev. 1.1
Apr. 2009
ETRON [ ETRON TECHNOLOGY, INC. ]
