EtronTech
Mode Register Set(MRS)
EM68916CWQA
The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls
CAS# latency, burst length, burst sequence, test mode, DLL reset, WR, and various vendor specific options
to make DDR2 SDRAM useful for various applications.The default value of the mode register is not defined,
therefore the mode register must be programmed during initialization for proper operation. The mode
register is written by asserting LOW on CS#, RAS#, CAS#, WE#, BA0 and BA1, while controlling the state
of address pins A0 - A12. The DDR2 SDRAM should be in all bank precharge state with CKE already HIGH
prior to writing into the mode register.The mode register set command cycle time (t
MRD
) is required to
complete the write operation to the mode register. The mode register contents can be changed using the
same command and clock cycle requirements during normal operation as long as all bank are in the
precharge state.The mode register is divided into various fields depending on functionality.
- Burst Length Field (A2, A1, A0)
This field specifies the data length of column access and selects the Burst Length.
- Addressing Mode Select Field (A3)
The Addressing Mode can be Interleave Mode or Sequential Mode. Both Sequential Mode and Interleave
Mode support burst length of 4 and 8.
-CAS# Latency Field (A6, A5, A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first read
data. The minimum whole value of CAS# Latency depends on the frequency of CK. The minimum whole
value satisfying the following formula must be programmed into this field.
t
CAC
(min)
≦
CAS# Latency X t
CK
- Test Mode field: A7; DLL Reset Mode field: A8
These two bits must be programmed to "00" in normal operation.
-
(BA0, BA1): Bank addresses to define MRS selection
.
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Field
Table 5. Mode Register Bitmap
BA1 BA0 A12
0
0
PD
WR
DLL
TM
CAS# Latency
BT
Burst Length
Mode Register
A8 DLL Reset
0
No
1
Yes
A7
0
1
Mode
Normal
Test
A3
0
1
Burst Type
Sequential
Interleave
A2
0
0
A1
1
1
A0
0
1
BL
4
8
A12 Active power down exit time
0
Fast exit (use t
XARD
)
1
Slow exit (use t
XARDS
)
BA1 BA0 MRS Mode
0
0
MR
0
1
EMR(1)
1
0
EMR(2)
1
1
EMR(3)
Write recovery for autoprecharge*1
A11 A10
A9
WR(cycles)
0
0
0
Reserved
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
1
0
1
6
1
1
0
Reserved
1
1
1
Reserved
A6
0
0
0
0
1
1
1
1
A5
0
0
1
1
0
0
1
1
A4
0
1
0
1
0
1
0
1
CAS# Latency
Reserved
Reserved
Reserved
3
4
5
6
Reserved
Note 1:.For
DDR2-533/667/800, WR min is determined by t
CK
(avg) max and WR max is determined by t
CK
(avg) min. WR
[cycles] = RU {t
WR
[ns]/t
CK
(avg)[ns]}, where RU stands for round up. The mode register must be programmed to this
value.This is also used with t
RP
to determine t
DAL
.
Etron Confidential
9
Rev. 1.1
Apr. 2009
ETRON [ ETRON TECHNOLOGY, INC. ]
