EM639325
EtronTech
Figure 26. Clock Suspension During Burst Write (Using CKE)
(Burst Length=4)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
CAx
DQM
DQ
Hi-Z
DAx0
Write
DAx1
DAx2
DAx3
Activate
Command
Bank A
Clock Suspend
3 Cycles
Clock Suspend
1 Cycle
Clock Suspend
2 Cycles
Command
Bank A
Don’t Care
Rev. 2.1
28
Aug. /2015