EM639325
EtronTech
Table 12. LVTTL Interface
Reference Level of Output Signals
Output Load
1.4V / 1.4V
Reference to the Under Output Load (B)
Input Signal Levels (VIH /VIL)
2.4V / 0.4V
1ns
Transition Time (Rise and Fall) of Input Signals
Reference Level of Input Signals
1.4V
1.4V
3.3V
50Ω
1.2KΩ
Output
Output
Z0=50Ω
870Ω
30pF
30pF
Figure 19.1 LVTTL D.C. Test Load (A)
Figure 19.2 LVTTL A.C. Test Load (B)
7. Transition times are measured between VIH and VIL. Transition (rise and fall) of input signals are in a fixed
slope (1 ns).
8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference levels.
9. If clock rising time is longer than 1 ns, (tR / 2 -0.5) ns should be added to the parameter.
10. Assumed input rise and fall time tT (tR & tF ) = 1 ns
If tR or tF is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns
should be added to the parameter.
11. Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to VDD and VDDQ (simultaneously) when CKE= “L”, DQM= “H” and all input
signals are held "NOP" state.
2) Start clock and maintain stable condition for minimum 200 µs, then bring CKE= “H” and, it is
recommended that DQM is held "HIGH" (VDD levels) to ensure DQ output is in high impedance.
3) All banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the
device.
* The Auto Refresh command can be issue before or after Mode Register Set command
Rev. 2.1
21
Aug. /2015
ETRON [ ETRON TECHNOLOGY, INC. ]
