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EM639325TS-5IG 参数 Datasheet PDF下载

EM639325TS-5IG图片预览
型号: EM639325TS-5IG
PDF下载: 下载PDF文件 查看货源
内容描述: [4M x 32 bit Synchronous DRAM (SDRAM)]
分类和应用: 动态存储器
文件页数/大小: 47 页 / 409 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
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EM639325  
EtronTech  
Table 11. Electrical Characteristics and Recommended A.C. Operating Conditions  
±
(VDD = 3.3V 0.3V, TA = -40~85°C) (Note: 5~8)  
-5I  
-6I  
-7I  
Unit Note  
Symbol  
A.C. Parameter  
Min. Max. Min. Max. Min. Max.  
tRC  
Row cycle time (same bank)  
55  
15  
-
-
60  
18  
-
-
63  
21  
-
-
tRCD  
tRP  
RAS# to CAS# delay (same bank)  
Precharge to refresh / row activate  
command (same bank)  
15  
10  
40  
-
-
18  
12  
42  
-
-
21  
14  
42  
-
-
ns  
tRRD  
tRAS  
Row activate to row active delay  
(different banks)  
Row activate to precharge time  
(same bank)  
100K  
100K  
100K  
Write recovery time  
2
1
-
-
2
1
-
2
1
-
tWR  
tCK  
CAS# to CAS# Delay time  
-
-
9
tCCD  
CL* = 2  
-
-
10  
6
-
10  
7
-
Clock cycle time  
tCK  
CL* = 3  
5
-
-
-
tCH  
tCL  
ns  
Clock high time  
Clock low time  
2
-
2.5  
2.5  
-
-
2.5  
2.5  
-
-
10  
10  
2
-
-
6
-
6.5  
5.4  
-
CL* = 2  
CL* = 3  
-
-
Access time from CLK  
(positive edge)  
tAC  
-
5
-
-
5.4  
-
-
tOH  
tLZ  
tHZ  
tIS  
Data output hold time  
2
2.5  
1
2.5  
1
9
Data output low impedance  
1
-
-
-
ns  
Data output high impedance CL* = 3  
Data/Address/Control Input set-up time  
Data/Address/Control Input hold time  
PowerDown Exit Setup Time  
-
5
-
-
5.4  
-
-
5.4  
-
8
1.5  
0.8  
1.5  
0.8  
1.5  
0.8  
10  
10  
tIH  
-
-
-
ns  
ns  
tCK  
µs  
ns  
t
IS+tCK  
-
-
tIS+ CK  
t
-
-
tIS+ CK  
t
-
-
tPDE  
tMRD  
tREFI  
tXSR  
2
-
2
-
2
-
Mode Register Set Command Cycle Time  
Refresh Interval Time  
15.6  
15.6  
15.6  
tRC+ IS  
t
-
tRC+ IS  
t
-
tRC+ IS  
t
-
Exit Self-Refresh to any Command  
*CL is CAS Latency.  
Note:  
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to  
the device.  
2. All voltages are referenced to VSS. VIH (Max) = 4.6V for pulse width 3ns. VIL(Min) = -1.0V for pulse  
width  
3ns.  
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the  
minimum value of tCK and tRC. Input signals are changed one time during every 2 tCK.  
4. These parameters depend on the output loading. Specified values are obtained with the output open.  
5. Power-up sequence is described in Note 11.  
6. A.C. Test Conditions  
Rev. 2.1  
20  
Aug. /2015  
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