EtronTech
EM638325
2Mega x 32 SDRAM
Figure 24.2. Precharge Termination of a Burst
(Burst Length=8 or Full Page, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
tCK2
High
RAS#
CAS#
WE#
BS0,1
A10
RAx
RAx
RAy
RAy
RAz
RAz
CAy
CAz
CAx
A0~A9
DQM
tRP
tWR
tRP
tRP
DQ
DAx0 DAxD1Ax2 DAx3
Ay0 Ay1 Ay2
Az0 Az1
Az2
Precharge
Command
Bank A
Precharge
Activate
Command
Bank A
Write
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Command
Bank A
Precharge Termination
Precharge Termination
of a Write Burst.
Writedata is masked.
of a Read Burst
Preliminary
70
Rev 1.4
Oct. 2005
ETRON [ ETRON TECHNOLOGY, INC. ]
