EtronTech
EM638325
2Mega x 32 SDRAM
Figure 24.1. Precharge Termination of a Burst (Burst Length=Full Page, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
RAy
RAy
RAz
CAy
RAx
CAx
RAz
CAz
A0~A9
DQM
tRP
tWR
tRP
Precharge
Termination of
a Read Burst.
DQ
DAz6 DAz7
DAx0 DAxD1Ax2 DAx3 DAx4
DAz0
DAz1 DAzD2Az3
DAz4 DAz5
Ay0 Ay1 Ay2
Read
Precharge
Command
Bank A
Write
Command
Bank A
Activate
Command
Bank A
Precharge
Command
Bank A
Precharge Termination
of a Write Burst.
Command
Bank A
Writedata is masked.
Write
Activate
Command
Bank A
Activate
Command
Bank A
Command
Bank A
Preliminary
69
Rev 1.4
Oct. 2005
ETRON [ ETRON TECHNOLOGY, INC. ]
