EtronTech
EM638325
2Mega x 32 SDRAM
Figure 6.3. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=3)
T0 T 1 T 2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK3
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
A0-A9
DQM
DQ
CAx
RAx
tHZ
Hi-Z
Ax0
Ax1
Ax2
Ax3
Clock Suspend
3 Cycles
Activate
Command
Bank A
Read
Command
Bank A
Clock Suspend Clock Suspend
1 Cycle
2Cycles
Note:
CKE to CLK disable/enable = 1 clock
Preliminary
27
Rev 1.4
Oct. 2005