EtronTech
EM638325
2Mega x 32 SDRAM
Figure 5. Self Refresh Entry & Exit Cycle
T0
T1
T2
T3
T4
T5
T7
T8
T9
T10 T11 T12 T13
T14 T15 T16
T17 T18
T19
T6
CLK
*Note 2
tRC(min) *Note 7
*Note 4
*Note 1
*Note 3
tPDE
CKE
CS#
tSRX
*Note 5
tIS
*Note 6
RAS#
CAS#
BS0,1
*Note 8
*Note 8
A0-A9
WE#
DQM
DQ
Hi-Z
Hi-Z
Self Refresh Enter
SelfRefresh Exit
AutoRefresh
Note: To Enter SelfRefresh Mode
1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in SelfRefresh mode as long as CKE stays "low".
4. Once the device enters SelfRefresh mode, minimum tRAS is required before exit from SelfRefresh.
To Exit SelfRefresh Mode
5. System clock restart and be stable before returning CKE high.
6. Enable CKE and CKE should be set high for minimum time of tSRX
.
7. CS# starts from high.
8. Minimum tRC is required after CKE going high to complete SelfRefresh exit.
9. 4096 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the
system uses burst refresh.
Preliminary
24
Rev 1.4
Oct. 2005
ETRON [ ETRON TECHNOLOGY, INC. ]
