EtronTech
Overview
2Mega x 32 SDRAM
EM638325
The EM638325 SDRAM is a high-speed CMOS synchronous DRAM containing 64 Mbits. It is internally configured
as a quad 512K x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock
signal, CLK). Each of the 512K x 32 bit banks is organized as 2048 rows by 256 columns by 32 bits. Read and write
accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number
of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then
followed by a Read or Write command.
The EM638325 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst
termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at
the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use.
By having a programmable mode register, the system can choose the most suitable modes to maximize its
performance. These devices are well suited for applications requiring high memory bandwidth.
Block Diagram
Col um n
Row Decoder
De co der
2048 X 256 X 32
CELL ARRAY
(BANK #0)
Sense
Ampl ifier
CL K
DLL
CL OCK
B U FFER
CON TRO L
SI G N A L
GEN ER A TO R
Sense
Row Decoder
CK E
Ampl ifier
C S#
R A S#
C A S#
W E#
COMMAND
D E C O D ER
M OD E
R EG I ST ER
2048 X 256 X 32
CELL ARRAY
(BANK #1)
Col um n
De coder
CO LU MN
C OU N T ER
A 10/A P
Col um n
Row Decoder
De co der
A0
A9
B S0
B S1
A D D R E SS
B U FFER
2048 X 256 X 32
CELL ARRAY
(BANK
#2)
Sense
Ampl ifier
R E F R E SH
C O U N TER
Sense
DQ
B U FFER
D Q0
│
D Q31
Row Decoder
Ampl ifier
2048 X 256 X 32
CELL ARRAY
(BANK
#3)
Col um n
De co der
D QM 0~3
Preliminary
2
Rev 1.4
Oct. 2005
ETRON [ ETRON TECHNOLOGY, INC. ]
