EtronTech
Pin Descriptions
1Mega x 32 SGRAM
EM637327
Table 1. Pin Details of EM637327
Symbol Type Description
CLK
Input
Clock:
CLK is driven by the system clock. All SGRAM input signals are sampled on the
positive edge of CLK. CLK also increments the internal burst counter and controls the
output registers.
Input
Clock Enable:
CKE activates(HIGH) and deactivates(LOW) the CLK signal. If CKE goes
low synchronously with clock(set-up and hold time same as other inputs), the internal clock
is suspended from the next clock cycle and the state of output and burst address is frozen
as long as the CKE remains low. When both banks are in the idle state, deactivating the
clock controls the entry to the Power Down and Self Refresh modes. CKE is synchronous
except after the device enters Power Down and Self Refresh modes, where CKE becomes
asynchronous until exiting the same mode. The input buffers, including CLK, are disabled
during Power Down and Self Refresh modes, providing low standby power.
Input
Bank Select:
BS defines to which bank the BankActivate, Read, Write, or BankPrecharge
command is being applied. BS is also used to program the 11th bit of the Mode and
Special Mode registers.
CKE
BS
A0-A10 Input
Address Inputs:
A0-A10 are sampled during the BankActivate command (row address
A0-A10) and Read/Write command (column address A0-A7 with A8 defining Auto
Precharge) to select one location out of the 512K available in the respective bank. During
a Precharge command, A8 is sampled to determine if both banks are to be precharged (A8
= HIGH). The address inputs also provide the op-code during a Mode Register Set or
Special Mode Register Set command.
CS#
Input
Chip Select:
CS# enables (sampled LOW) and disables (sampled HIGH) the command
decoder. All commands are masked when CS# is sampled HIGH. CS# provides for
external bank selection on systems with multiple banks. It is considered part of the
command code.
Input
Row Address Strobe:
The RAS# signal defines the operation commands in conjunction
with the CAS# and WE# signals and is latched at the positive edges of CLK. When RAS#
and CS# are asserted "LOW" and CAS# is asserted "HIGH," either the BankActivate
command or the Precharge command is selected by the WE# signal. When the WE# is
asserted "HIGH," the BankActivate command is selected and the bank designated by BS is
turned on to the active state. When the WE# is asserted "LOW," the Precharge command
is selected and the bank designated by BS is switched to the idle state after the precharge
operation.
Input
Column Address Strobe:
The CAS# signal
conjunction with the RAS# and WE# signals and
When RAS# is held "HIGH" and CS# is asserted
asserting CAS# "LOW." Then, the Read or Write
"LOW" or "HIGH."
defines the operation commands in
is latched at the positive edges of CLK.
"LOW," the column access is started by
command is selected by asserting WE#
RAS#
CAS#
WE#
Input
Write Enable:
The WE# signal defines the operation commands in conjunction with the
RAS# and CAS# signals and is latched at the positive edges of CLK. The WE# input is
used to select the BankActivate or Precharge command and Read or Write command.
Input
Define Special Function:
The DSF signal defines the operation commands in conjunction
with the RAS# and CAS# and WE# signals and is latched at the positive edges of CLK.
The DSF input is used to select the masked write disable/enable command and block write
command, and the Special Mode Register Set cycle.
DSF
Preliminary
3
August 1999
ETRON [ ETRON TECHNOLOGY, INC. ]
