EtronTech
EM636327
DSF
DQM0
Q
D
DRAM
CELL
CK
BankActivate
command
DQ7
DQ6
MR7
MR6
MR5
MR4
MR3
MR2
MR1
MR0
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
0 = Masked
1 = Not Masked
Note:
Only the lower byte is shown. The operation is identical for other bytes.
Write Per Bit (I/O Mask) Block Diagram
A write burst without the auto precharge function may be interrupted by a subsequent
Write/Block Write, BankPrecharge/PrechargeAll, or Read command before the end of the burst
length. An interrupt coming from Write/Block Write command can occur on any clock cycle
following the previous Write command (refer to the following figure).
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
NOP
NOP
COMMAND
NOP
WRITE A
WRITE B
NOP
NOP
NOP
1 Clk Interval
DIN DIN B
A
DIN B
DIN B
DIN B
3
DQ's
0
0
1
2
Write Interrupted by a Write
(Burst Length = 4, CAS# Latency = 1, 2, 3)
The Read command that interrupts a write burst without auto precharge function should be
issued one cycle after the clock edge in which the last data-in element is registered. In order to
avoid data contention, input data must be removed from the DQs at least one clock cycle before the
Preliminary
1998
December
10
ETRON [ ETRON TECHNOLOGY, INC. ]
