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EM636327Q-7 参数 Datasheet PDF下载

EM636327Q-7图片预览
型号: EM636327Q-7
PDF下载: 下载PDF文件 查看货源
内容描述: 512K ×32高速同步图形DRAM ( SGRAM ) [512K x 32 High Speed Synchronous Graphics DRAM(SGRAM)]
分类和应用: 动态存储器
文件页数/大小: 78 页 / 1387 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
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EtronTech  
EM636327  
14 Burst Stop command  
(RAS# = "H", CAS# = "H", WE# = "L", DSF = "L")  
The Burst Stop command is used to terminate either fixed-length or full-page bursts. This  
command is only effective in a read/write burst without the auto precharge function. The terminated  
read burst ends after a delay equal to the CAS# latency (refer to the following figure). The  
termination of a write burst is shown in the following figure.  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
CLK  
READ A  
NOP  
NOP  
NOP  
COMMAND  
NOP  
NOP  
Burst Stop  
DOUT A  
NOP  
NOP  
The burst ends after a delay equal to the CAS# latency.  
CAS# latency=1  
DOUT A  
DOUT A  
DOUT A  
0
1
2
3
t
, DQ's  
CK1  
CAS# latency=2  
, DQ's  
DOUT A  
DOUT A  
DOUT A  
2
DOUT A  
3
0
1
t
CK2  
CAS# latency=3  
DOUT A  
0
DOUT A  
DOUT A  
DOUT A  
3
1
2
t
, DQ's  
CK3  
Termination of a Burst Read Operation  
¡ Ö  
4, CAS# Latency = 1, 2, 3)  
(Burst Length  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
CLK  
NOP  
NOP  
NOP  
COMMAND  
NOP  
WRITE A  
NOP  
Burst Stop  
don't care  
NOP  
NOP  
CAS# latency=1, 2, 3  
DQ's  
DIN A  
DIN  
A
DIN A  
2
1
0
Input data for the Write is masked.  
Termination of a Burst Write Operation  
(Burst Length = X, CAS# Latency = 1, 2, 3)  
15 Device Deselect command  
(CS# = "H")  
The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE#  
and Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar  
to the No Operation command.  
16 AutoRefresh command (refer to Figures 3 & 4 in Timing Waveforms)  
(RAS# = "L", CAS# = "L", WE# = "H", DSF = "L", CKE = "H", BS, A0-A9 = Don't care)  
The AutoRefresh command is used during normal operation of the SGRAM and is analogous to  
CAS#-before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it  
must be issued each time a refresh is required. The addressing is generated by the internal refresh  
controller. This makes the address bits a "don't care" during an AutoRefresh command. The internal  
refresh counter increments automatically on every auto refresh cycle to all of the rows. The refresh  
operation must be performed 2048 times within 32ms. The time required to complete the auto  
refresh operation is specified by tRC(min.). To provide the AutoRefresh command, both banks need  
to be in the idle state and the device must not be in power down mode (CKE is high in the previous  
cycle). This command must be followed by NOPs until the auto refresh operation is completed. The  
precharge time requirement, tRP(min), must be met before successive auto refresh operations are  
performed.  
Preliminary  
1998  
December  
17