EtronTech
EM636165
1M x 16 SDRAM
Figure 19.1. Full Page Write Cycle
(Burst Length=Full Page, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
High
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RBx
RAx
RBy
RBy
RAx
CAx RBx
CBx
A0~A9
DQM
Hi-Z
DBx DBx+1
DAx+1
DBx+3
DQ
DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx
DBx+2
DBx+4 DBx+5 DBx+6 DBx+7
Data is ignored
Activate
Command
Bank B
Activate
Command
Bank A
Write
Command
Bank B
Precharge
Command
Bank B
Full Page burst operation does
not terminate when the burst
length is satisfied; the burst counter
increments and continues bursting
beginning with the starting address.
Burst Stop
Command
The burst counter wraps
Activate
Command
Bank B
from the highest order
page address back to zero
during this time interval
Write
Command
Bank A
Preliminary
64
Rev. 2.7 Mar. 2006
ETRON [ ETRON TECHNOLOGY, INC. ]
