EtronTech
EM636165
1M x 16 SDRAM
Figure 18.1. Full Page Read Cycle
(Burst Length=Full Page, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
High
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBx
RBx
RBy
RBy
CBx
RAx CAx
tRRD
A0~A9
DQM
tRP
Hi-Z
DQ
Bx+6 Bx+7
Ax+1
Ax
Ax+2
Bx+1
Bx+2 Bx+3 Bx+4 Bx+5
Ax-2 Ax-1 Ax
Ax+1 Bx
Activate
Activate
Bank B
Precharge
Read
Command
Bank B
Command Command
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Bank A
Read
Burst Stop
Command
Activate
Command
Bank B
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address.
Command
Bank A
Preliminary
61
Rev. 2.7 Mar. 2006
ETRON [ ETRON TECHNOLOGY, INC. ]
