EtronTech
EM636165
1M x 16 SDRAM
Electrical Characteristics and Recommended A.C. Operating Conditions
±
(VDD = 3.3V 0.3V, Ta = -0~70 C) (Note: 5, 6, 7, 8)
°
- 5/55/6/7/7L/8/10
Symbol
A.C. Parameter
Row cycle time
Min.
Max.
Unit Note
tRC
48/48/54/63/63/72/90
9
(same bank)
tRCD
RAS# to CAS# delay
(same bank)
15/16/16/16/16/16/30
9
ns
9
tRP
Precharge to refresh/row activate
command (same bank)
15/16/16/1616//16/30
10/11/12/14/14/16/20
tRRD
Row activate to row activate delay
(different banks)
9
tRAS
tWR
Row activate to precharge time
(same bank)
30/32/36/42/42/48/60
100,000
Write recovery time
Cycle
1
tCK1
tCK2
tCK3
tCH
CL* = 1
-/19/20/20/20/20/30
-/7/7.5/8/8/8/15
5/5.5/6/7/7/8/10
2/2/2/2.5/2.5/3/3.5
2/2/2/2.5/2.5/3/3.5
10
Clock cycle time
CL* = 2
CL* = 3
ns
11
11
Clock high time
Clock low time
tCL
tAC1
tAC2
tAC3
tCCD
tOH
tLZ
Access time from CLK
(positive edge)
CL* = 1
CL* = 2
CL* = 3
-/7/8/13/13/18/27
-/5.5/6/6.5/6.5/7/12
4.5/5/5/5.5/5.5/6.5/7.5
11
10
CAS# to CAS# Delay time
Data output hold time
1
Cycle
1.8/2/2/2/2/2/3
1/1/1/1/1/2/2
Data output low impedance
Data output high impedance
tHZ
3/3.5/4/5/5/6/8
8
tIS
Data/Address/Control Input set-up time
Data/Address/Control Input hold time
PowerDown Exit set-up time
Refresh time
2/2/2/2/2/2.5/3
1
ns
11
11
tIH
tPDE
tREF
2/2/2/2/2/2.5/3
64
ms
* CL is CAS# Latency.
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device.
2. All voltages are referenced to VSS. VIH(Max)=4.6 for pulse width≤5ns.VIL(Min)=-1.5Vfor pulse width≤5ns.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time during tCK.
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power-up sequence is described in Note 12.
Preliminary
20
Rev. 2.7 Mar. 2006
ETRON [ ETRON TECHNOLOGY, INC. ]
