EtronTech
EM636165-XXI
1M x 16 SDRAM
Figure 13.1. Read and Write Cycle
(Burst Length=4, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK1
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RAx CAx
CAy
CAz
A0~A9
DQM
Hi-Z
Az3
DQ
Ax0 Ax1 Ax2
Ax3
DAy0DAy1
DAy3
Az0 Az1
Read
Command
Bank A
Activate
Command
Bank A
Write
Command
Bank A
The Read Data
Precharge
Command
Bank B
The Write Data
is Maskedwith a
Two Clock
is Maskedwith a
Zero Clock
Latency
Read
Latency
Command
Bank A
Preliminary
45
Rev. 1.1 Apr. 2005