Document No.: FT_000288
FT232H SINGLE CHANNEL HI-SPEED USB TO MULTIPURPOSE UART/FIFO IC
Datasheet Version 1.8
Clearance No.: FTDI #199
4.10 CPU-style FIFO Interface Mode Description
CPU-style FIFO interface mode is designed to allow a CPU to interface to USB via the FT232H. This mode
is enabled in the external EEPROM. The interface is achieved using a chip select bit (CS#) and address bit
(A0). When the FT232H is in CPU-style Interface mode, the IO signal lines are configured as given in
Table 4.6. This mode uses a combination of CS# and A0 to determine the operation to be carried out.
The following Truth-Table 4.7 gives the decode values for particular operations.
CS#
A0
X
RD#
WR#
1
0
0
X
X
0
Read Data Pipe
Read Status
Write Data Pipe
Send Immediate
1
Table 4.6 CPU-Style FIFO Interface Operation Select
The Status read is shown in Table 4.7
Data Bit
bit 0
Data
Status
1
1
1
1
X
X
X
X
Data available (=RXF)
bit 1
Space available (=TXE)
bit 2
Suspend
bit 3
Configured
bit 4
X
X
X
X
bit 5
bit 6
bit 7
Table 4.7 CPU-Style FIFO Interface Operation Read Status Description
Note that bits 7 to 4 can be arbitrary values and that X= not used.
The timing of reading and writing in this mode is shown in Figure 4.21 and Table 4.8.
Figure 4.21 CPU-Style FIFO Interface Operation Signal Waveforms.
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