ESMT
SIMPLIFIED TRUTH TABLE
COMMAND
Mode Register set
Register
Extended Mode Register
set
Auto Refresh
Refresh
Self
Refresh
Entry
Exit
Bank Active & Row Addr.
Read &
Column Address
Write &
Column Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
H
H
X
X
L
L
H
L
Exit
Entry
Precharge Power Down Mode
Exit
DQM
No Operating Command
Entry
Deep Power Down Mode
Exit
L
H
H
H
L
X
L
H
H
L
L
X
H
L
H
H
L
X
H
L
H
L
H
L
X
V
X
X
H
X
V
X
X
H
H
X
X
H
H
X
X
H
L
X
H
H
X
V
X
X
H
X
V
L
L
X
V
X
X
H
X
V
X
X
X
V
X
X
X
X
X
H
X
L
H
L
L
X
H
H
X
H
L
H
X
X
L
L
L
H
H
H
L
L
L
H
X
L
H
L
H
X
H
L
H
H
X
H
H
X
X
X
X
X
L
L
L
L
X
CKEn-1
CKEn
CS RAS CAS
WE
M52D128168A
DQM BA0 A10/AP
BA1
A11,
A9~A0
Note
OP CODE
1,2
3
X
3
3
X
V
V
Row Address
L
H
L
H
X
V
X
L
H
X
Column
Address
(A0~A8)
Column
Address
(A0~A8)
3
4
4,5
4
4,5
6
V
Burst Stop
Precharge
Bank Selection
All Banks
Entry
Clock Suspend or
Active Power Down
H
L
X
X
X
X
X
X
7
(V = Valid, X = Don’t Care. H = Logic High, L = Logic Low)
Note:
1.OP Code: Operating Code
A0~A11 & BA0~BA1: Program keys. (@ MRS). BA1=0 for MRS and BA1=1 for EMRS
2.MRS/EMRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS/EMRS.
3.Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge of command is meant by “Auto”.
Auto/self refresh can be issued only at all banks idle state.
4.BA0~BA1: Bank select addresses.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If both BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank B is selected.
If both BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected
If A10/AP is “High” at row precharge , BA0 and BA1 is ignored and all banks are selected.
5.During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t
RP
after the end of burst.
6.Burst stop command is valid at every burst length.
7.DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (write DQM latency is 0), but
makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009
Revision: 1.3
7/48
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
