M32L1632512A
3.Auto refresh functions as same as CBR refresh of DRAM.
The automatical precharge without Row precharge of command is meant by “Auto”.
Auto/self refresh can be issued only at both banks precharge state.
4.A10 : Bank select address.
If “Low” at read, (block) write, Row active and precharge, bank A is selected.
If “High” at read, (block) write, Row active and precharge, bank B is selected.
If A9 is “High” at Row precharge, A10 is ignored and both banks are selected.
5.It is determined at Row active cycle.
whether Normal/Block write operates in write per bit mode or not.
For A bank write, at A bank Row active, for B bank write, at B bank Row active.
Terminology : Write per bit = I/O mask
(Block) Write with write per bit mode = Masked (Block) Write
6.During burst read or write with auto precharge, new read/(block) write command cannot be issued.
Another bank read/(block) write command can be issued at tRP after the end of burst.
7.Burst stop command is valid for all burst length.
8.DQM sampled at positive going edge of a CLK.
masks the data-in at the very CLK (Write DQM latency is 0)
but makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)
9.Graphic features added to SDRAM’s original features.
If DSF is tied to low, graphic functions are disabled and chip operates as a 16M SDRAM with 32
DQ’s.
SGRAM vs SDRAM
SDRAM Function
MRS
Bank Active
Write
DSF
L
H
L
H
L
H
Bank Active
With
Write per bit Write per bit
Disable Enable
Bank Active
With
SGRAM
Function
Normal
Write
Block
Write
MRS
SMRS
If DSF is low. SGRAM functionality is identical to SDRAM functionality.
SGRAM can be uesed as an unified memory by the appropriate DSF control
SGRAM = Graphic Memory + Main Memory.
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address
Function
A10
A9
A8
A7
A6
A5
A4
A3
BT
A2
A1
A0
RFU
W.B.L
TM
CAS Latency
Burst Length
(Note1)
(Note2)
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6 10/54
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
