ESMT
M24L28256SA
AC Test Loads and Waveforms
Parameters
3.0V (VCC
22000
22000
11000
1.50
)
Unit
Ω
Ω
Ω
V
R1
R2
RTH
VTH
Switching Characteristics Over the Operating Range [8]
-55
-70
Parameter
Read Cycle
tRC
tAA
tOHA
tACE
Description
Unit
Min.
55[12]
5
Max.
Min.
70
Max.
Read Cycle Time
ns
ns
ns
ns
Address to Data Valid
Data Hold from Address Change
55
70
10
55
25
70
35
CE LOW
tDOE
ns
ns
ns
ns
ns
ns
OE LOW to Data Valid
OE LOW to Low Z[9, 10]
OE HIGH to High Z[9, 10]
CE LOW
tLZOE
tHZOE
tLZCE
tHZCE
5
2
5
5
25
25
25
0
25
10
CE HIGH
Address Skew
tSK[12]
Write Cycle [11]
tWC
Write Cycle Time
55
45
70
55
ns
ns
tSCE
CE LOW
tAW
tHA
tSA
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
45
0
0
55
0
0
ns
ns
ns
tPWE
40
55
ns
WE Pulse Width
tSD
Data Set-Up to Write End
25
25
ns
tHD
Data Hold from Write End
0
5
0
5
ns
ns
ns
tHZWE
tLZWE
25
25
WE LOW to High-Z[9, 10]
WE HIGH to Low-Z[9, 10]
Notes:
8. Test conditions assume signal transition time of 1V/ns or higher, timing reference levels of VCC(typ)/2, input pulse levels of 0V
to VCC(typ), and output loading of the specified IOL/IOH and 30-pF load capacitance
9. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
10. High-Z and Low-Z parameters are characterized and are not 100% tested.
11. The internal write time of the memory is defined by the overlap of WE , CE = VIL, . All signals must be ACTIVE to initiate a
write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be
referenced to the edge of the signal that terminates write.
12. To achieve 55-ns performance, the read access should be CE controlled. In this case tACE is the critical parameter and tSK
is satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be
stable within 10 ns after the start of the read cycle.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.1 4/12
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
