M24L28256SA 参数 Datasheet PDF下载

ESMT

Switching Waveforms (continued)

Write Cycle 1 (

WE

Controlled)[10,11, 15, 16, 17]

M24L28256SA

Write Cycle 2 (

CE Controlled) [9, 10, 15, 16, 17]

Notes:

15.Data I/O is high impedance if OE

≥

V

IH

.

16. If Chip Enables go INACTIVE simultaneously with

WE

=HIGH, the output remains in a high-impedance state.

17.During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.

Elite Semiconductor Memory Technology Inc.

Publication Date

:

Jul. 2008

Revision

:

1.1

6/12