M24L28256DA-70BEG 参数 Datasheet PDF下载

ESMT

Switching Waveforms (continued)

Write Cycle No.1 (

WE

Controlled)[9,10, 14, 15, 16]

M24L28256DA

Write Cycle 2 (

CE

1

or CE

2

Controlled) [9, 10, 14, 15, 16]

Notes:

14.Data I/O is high impedance if OE

≥

V

IH

.

15. If Chip Enables go INACTIVE simultaneously with

WE

=HIGH, the output remains in a high-impedance state.

16.During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.

Elite Semiconductor Memory Technology Inc.

Publication Date

:

Jul. 2007

Revision

:

1.0

6/10