ESMT
AC Test Loads and Waveforms
M24L28256DA
Parameters
R1
R2
R
TH
V
TH
3.0V (V
CC
)
22000
22000
11000
1.50
Unit
Ω
Ω
Ω
V
Switching Characteristics
(Over the Operating Range) [7]
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
SK[
11]
Write Cycle
[10]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Description
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW and CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[8, 9]
OE HIGH to High Z[8, 9]
CE
1
LOW and CE
2
HIGH to LOW Z[8, 9]
CE
1
HIGH and CE
2
LOW to HIGH Z[ 8, 9]
Address Skew
Write Cycle Time
CE
1
LOW and CE
2
HIGH to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE
Pulse Width
-55
Min.
55[11]
55
5
55
25
5
25
5
25
0
55
45
45
0
0
40
25
0
25
5
5
70
55
55
0
0
55
25
0
5
5
10
Max.
Min.
70
-70
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
70
35
25
25
10
Data Set-Up to Write End
Data Hold from Write End
WE
LOW to High-Z[8, 9]
WE
HIGH to Low-Z[8, 9]
25
ns
ns
Notes:
7. Test conditions assume signal transition time of 1V/ns or higher, timing reference levels of V
CC(typ)
/2, input pulse levels of 0V
to V
CC(typ)
, and output loading of the specified I
OL
/I
OH
and 30-pF load capacitance
8. t
HZOE
, t
HZCE
, and t
HZWE
transitions are measured when the outputs enter a high-impedance state.
9. High-Z and Low-Z parameters are characterized and are not 100% tested.
10. The internal write time of the memory is defined by the overlap of
WE
, CE
1
= V
IL
, and CE
2
=V
IH
. All signals must be
ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold
timing should be referenced to the edge of the signal that terminates write.
11. To achieve 55-ns performance, the read access should be CE controlled. In this case t
ACE
is the critical parameter and t
SK
is satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be
stable within 10 ns after the start of the read cycle.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2007
Revision
:
1.0
4/10
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
