ESMT
M24L216128SA
Switching Waveforms (continued)
Write Cycle 1 (WE Controlled)[12, 13, 18, 19, 20]
Write Cycle 2 (CE Controlled)[12, 13, 18, 19, 20]
Notes:
18.Data I/O is high impedance if OE ≥ VIH.
19.If Chip Enable goes INACTIVE with WE = VIH, the output remains in a high-impedance state.
20.During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.2 7/14