ESMT
Variable Address Mode Register (VAR) Update[5, 6]
M24L16161ZA
Deep Sleep Mode—Entry/Exit[7]
VAR Update and Deep Sleep Mode Timing[5, 6]
Parameter
t
ZZWE
t
CDR
t
R
[7]
t
ZZMIN
Notes:
5. OE and the data pins are in a don’t care state while the device is in variable address mode.
6. All other timing parameters are as shown in the data sheets.
7. t
R
applies only in the deep sleep mode.
Description
ZZ
LOW to Write Start
Min.
0
200
8
Max.
1
Unit
µs
ns
µs
µs
Chip deselect to
ZZ
LOW
Operation Recovery Time (Deep Sleep Mode only)
Deep Sleep Mode Time
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2007
Revision
:
1.0
4/15