ESMT
BALL CONFIGURATION (TOP VIEW)
(BGA48, 6mmX8mmX1mm Body, 0.8mm Ball Pitch)
1
A
B
C
D
E
F
G
H
BLE
DQ
8
DQ
9
V
SSQ
V
CCQ
DQ
14
DQ
15
A
18
2
OE
BHE
DQ
10
DQ
11
DQ
12
DQ
13
A
19
A
8
3
A
0
A
3
A
5
A
17
NC
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
DQ
1
DQ
3
DQ
4
DQ
5
6
ZZ
DQ
0
DQ
2
V
CC
V
SS
DQ
6
DQ
7
NC
M24L16161ZA
WE
A
11
Ball Function Description
Ball Name
A[19:0]
CE
BLE
Type
Input
Input
Input
Input
Input
Input
Input
Input / Output
-
Supply
Supply
Supply
Supply
Description
Address inputs: Inputs for the address accessed during READ or WRITE operations. The
address lines are also used to define the value to be loaded into the RCR.
Chip enable: Activates the device when LOW. When CE is HIGH, the device is disabled
and goes into standby power mode.
Lower byte enable: DQ[7:0].
Output enable: Enables the output buffers when LOW. When OE is HIGH, the output
buffers are disabled.
Upper byte enable: DQ[15:8].
Write enable: Enables WRITE operations when LOW.
Sleep enable: When
ZZ
is LOW, the RCR can be loaded or the device can enter one of
two low-power modes (DPD or PAR).
Data inputs/outputs.
Not internally connected.
Device power supply: Power supply for device core operation.
I/O power supply: Power supply for input/output buffers.
V
SS
must be connected to ground.
V
SSQ
must be connected to ground.
OE
BHE
WE
ZZ
DQ[15:0]
NC
V
CC
V
CCQ
V
SS
V
SSQ
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Dec. 2010
Revision: 1.0
3/21
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
