ESMT
Switching Characteristics
Over the Operating Range [12, 13, 14, 15, 18]
Parameter
Read Cycle
t
RC
[17]
t
CD
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
DBE
t
LZBE
t
HZBE
Write Cycle[15]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Read Cycle Time
Chip Deselect Time CE ,
BLE
/
BHE
High Pulse Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z [13, 14, 16]
OE HIGH to High Z [13, 14, 16]
CE LOW Low Z [13, 14, 16]
CE HIGH to High Z [13, 14, 16]
BLE
/
BHE
LOW to Data Valid
BLE
/
BHE
LOW to Low Z[13, 14, 16]
BLE
/
BHE
HIGH to High Z[13, 14, 16]
M24D16161ZA
Description
-70
Min.
70
15
10
70
35
5
25
10
25
70
5
25
70
60
15
60
0
0
50
60
25
0
10
25
40000
Max.
40000
70
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
CE LOW to Write End
Chip Deselect Time CE ,
BLE
/
BHE
High Pulse Time
Address Hold from Write End
Address Set-Up to Write Start
WE
Pulse Width
BLE
/
BHE
LOW to Write End
Data Set-Up to Write End
Data Hold from Write End
WE
LOW to High-Z[13, 14, 16]
WE
HIGH to Low-Z[13, 14, 16]
Notes:
12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference
levels of V
CC
/2, input pulse levels of 0V to V
CC
, and output loading of the specified I
OL
/I
OH
as shown in the “AC Test Loads and
Waveforms” section.
13. At any given temperature and voltage conditions t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and
t
HZWE
is less than t
LZWE
for any given device. All low-Z parameters will be measured with a load capacitance of 30 pF (1.8V).
14. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high-impedance state.
15. The internal Write time of the memory is defined by the overlap of
WE
, CE = V
IL
,
BHE
and/or
BLE
= V
IL
. All signals
must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up
and hold timing should be referenced to the edge of the signal that terminates the write.
16. High-Z and Low-Z parameters are characterized and are not 100% tested.
17. If invalid address signals shorter than min. t
RC
are continuously repeated for 40 µs, the device needs a normal read timing
(t
RC
) or needs to enter standby state at least once in every 40 µs.
18. In order to achieve 70 ns performance, the read access must be CE controlled. That is, the addresses must be stable prior
to CE going active.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2007
Revision
:
1.0
9/15
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
