ESMT
M24D16161ZA
Switching Waveforms (continued)
Write Cycle 4 (BHE/BLE Controlled, OE LOW)[15, 19, 22, 23]
Truth Table[24, 25]
Inputs/Outputs
High Z
High Z
Mode
Power
CE
H
X
L
L
OE
X
X
X
L
ZZ
H
H
H
H
WE
X
X
X
H
BHE
X
H
H
L
BLE
X
H
H
L
Deselect/Power-down
Deselect/Power-down
Deselect/Power-down
Read
Standby (ISB
Standby (ISB
Standby (ISB
)
)
)
High Z
Data Out (I/O0-I/O15)
Data Out (I/O0-I/O7);
I/O8-I/O15 In High Z
Data Out (I/O8-I/O15);
I/O0-I/O7 In High Z
High Z
Active (ICC
)
H
H
L
L
H
H
L
L
H
L
L
Read
Read
Active (ICC
)
H
Active (ICC
)
H
H
H
L
L
L
H
H
H
H
H
H
L
H
L
L
L
H
Output Disabled
Output Disabled
Output Disabled
Write (Upper Byte and Lower
Byte
Active (ICC
Active (ICC
Active (ICC
)
)
)
High Z
High Z
H
H
H
L
L
L
L
L
X
X
X
X
X
L
H
L
L
L
Data In (I/O0-I/O15)
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
Data In (I/O0-I/O7);
I/O8-I/O15 In High Z
Data In (I/O8-I/O15);
I/O0-I/O7 In High Z
Write (Lower Byte Only)
Write (Upper Byte Only)
L
L
H
H
X
Write (Variable Address
Mode Register)
H
H
X
X
H
X
Data In (A0-A4)
High Z
Deep Sleep
(IZZ)/Stand by
L
Deep Power-down/PAR
Notes:
24.H = Logic HIGH, L = Logic LOW, X = Don’t Care.
25.During ZZ = L and CE = H, Mode depends on how the VAR is set up either in PAR or Deep Sleep Modes.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0 13/15
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
