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M24D16161ZA-70BIG 参数 Datasheet PDF下载

M24D16161ZA-70BIG图片预览
型号: M24D16161ZA-70BIG
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆位( 1M ×16 )伪静态RAM [16-Mbit (1M x 16) Pseudo Static RAM]
分类和应用:
文件页数/大小: 15 页 / 264 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT
Pin Configuration[2, 3]
48-ball VFBGA
Top View
M24D16161ZA
Product Portfolio
Product
M24D16161ZA
Min.
1.7
V
CC
Range (V)
Typ.
1.8
Max.
1.95
Speed(ns)
70
Power Dissipation
Operating I
CC
(mA)
Standby I
SB2
(µA)
f = 1MHz
f = f
MAX
Typ.[4]
Max.
Typ.[4]
Max.
Typ. [4]
Max.
3
5
18
20
55
70
Stand-By Mode, as configured by the user through the
settings in the Variable Address Register.
Once
ZZ
returns high in this mode, the PSRAM goes back
too perating in full address refresh. Please refer to “Variable
Address Space Register (VAR)” on page4 for the protocol to
turn off sections of the memory in Stand-By mode. If the VAR
register is not updated after the power up, the PSRAM will be
in its default state. In the default state the whole memory
array will be refreshed in the Stand-By Mode. The 16-Mbit is
divided into four 4-Mbit sections allowing certain sections to
be active (i.e., refreshed).
Deep Sleep Mode
In this mode, the data integrity in the PSRAM is not
guaranteed. This mode can be used to lower the power
consumption of the PSRAM in an application. This mode can
be enabled and disabled through VAR similar to the RMS and
PAR mode. Deep Sleep Mode is activated by driving
ZZ
LOW. The device stays in the deep sleep mode until
ZZ
is
driven HIGH.
Low-Power Modes
At power-up, all four sections of the die are activated and the
PSRAM enters into its default state of full memory size and
refresh space. This device provides four different Low-Power
Modes.
1.Reduced Memory Size Operation
2.Partial Array Refresh
3.Deep Sleep Mode
4.Temperature Controlled Refresh
Reduced Memory Size Operation
In this mode, the 16 Mb PSRAM can be operated as a
12-Mbit,8-Mbit or a 4-Mbit memory block. Please refer to
“Variable Address Space Register (VAR)” on page4 for the
protocol to turn on/off sections of the memory. The device
remains in RMS mode until changes to the Variable Address
Space register are made to revert back to a complete 16-Mbit
PSRAM.
Partial Array Refresh
The Partial Array Refresh mode allows customers to turn off
sections of the memory block in the Stand-by mode (with
ZZ
tied low) to reduce standby current. In this mode the PSRAM
will only refresh certain portions of the memory in the
Notes:
2.Ball H6, E3 can be used to upgrade to 32M and 64M density respectively.
3.NC “no connect” - not connected internally to the die.
4.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ.)
,
T
A
= 25°C. Tested initially and after any design changes that may affect the parameter.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2007
Revision
:
1.0
3/15