ESMT
Parameter
Symbol
Test Condition
t
CK
= t
CK
(IDD);
Refresh command every t
RFC
(IDD) interval;
CKE is HIGH, CS is HIGH between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Self Refresh Mode;
CLK and CLK at 0V; CKE
≤
0.2V;
Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING
All bank interleaving Reads, I
OUT
= 0mA;
BL = 4, CL= CL (IDD), AL = t
RCD
(IDD) – 1 × t
CK
(IDD);
t
CK
= t
CK
(IDD), t
RC
= t
RC
(IDD),
t
RRD
= t
RRD
(IDD), t
RCD
= 1 × t
CK
(IDD);
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are STABLE during Deslects;
Data pattern is the same as IDD4W;
-3
M14D5121632A
Operation Temperature Condition (T
C
) -40
°
C~95
°
C
Version
Unit
Auto Refresh Current
IDD5
100
mA
Self Refresh Current
IDD6
6
mA
Operating Current
(Bank interleaving)
IDD7
230
mA
Note:
1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Input Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS and /DQS, IDD values must be met with all combinations of EMRS bits 10 and 11.
5. Definitions for IDD:
LOW is defined as V
IN
≤
V
IL
(AC) (max.).
HIGH is defined as V
IN
V
IH
(AC) (min.).
STABLE is defined as inputs stable at a HIGH or LOW level.
FLOATING is defined as inputs at V
REF
= V
DDQ
/2
SWITCHING is defined as:
Address and control signal Inputs are changed between HIGH and LOW every other clock cycle (once per two clocks), and
DQ (not including mask or strobe) signal inputs are changed between HIGH and LOW every other data transfer (once per
clock).
6. When T
C
≧ +85 ℃,
IDD6 must be derated by 80%.
IDD6 will increase by this amount if T
C
≧ +85 ℃
and double refresh option is still enabled.
7. AC Timing for IDD test conditions
For purposes of IDD testing, the following parameters are to be utilized.
-3
Parameter
CL (IDD)
tRCD (IDD)
tRC (IDD)
tRRD (IDD)
tCK (IDD)
tRAS (IDD) min.
tRAS (IDD) max.
tRP (IDD)
tRFC (IDD)
DDR2-667
(5-5-5)
5
15
60
10
3
45
70000
15
105
Unit
t
CK
ns
ns
ns
ns
ns
ns
ns
ns
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009
Revision : 1.1
7/59
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
